A typical semiconductor manufacturing process involves selectively patterning a dielectric layer to form a three dimensional pattern of openings (such as trenches and vias) which will be filled with various metal conductors to provide the contacts, vias and interconnects between semiconductor devices.
With increasing down-scaling of integrated circuits and the increasingly demanding requirements to the speed of integrated circuits, semiconductor devices, such as transistors, need higher drive currents with increasingly smaller dimensions. However, at the smaller technology nodes of semiconductor manufacturing, such as the 10 nanometer (nm) class node, the patterned openings in a dielectric become increasingly difficult to fill. This is particularly the case when the aspect ratios of the trenches or vias become large, e.g., 10 or greater.
Accordingly, cobalt (Co) filling processes, such as electroplating, electro-less plating, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) and the like, have become more widely implemented in state of the art multilayer semiconductor manufacturing applications. This is due to cobalt's superior filling capabilities compared to other metals such as tungsten (W) or copper (Cu). Additionally, at the 10 nm scale, Co resistivity approaches that of W and Cu. Cobalt plating has been used in the formation of source/drain contacts, gate contacts, trench silicide contacts, conductive interconnections between semiconductor devices and the like.
However, prior art cobalt filling processes require both a protective barrier layer and a seed liner layer prior to plating. The barrier layer, which is typically tantalum nitride or titanium nitride, is required to protect the dielectric from damage caused by cobalt diffusing into the dielectric. The seed liner layer is required to provide a site for the cobalt filling to adhere or bond to.
Problematically, as semiconductors become increasingly smaller, the barrier layer and liner layer take up a significant volume within the patterned openings. Indeed, at the 10 nm size class, the barrier layer alone can occupy up to one third (⅓) of the volume of a trench or via, which can significantly reduce conductivity and performance. Moreover, since the trench and via sizes are so small, the barrier layer and the seed (or liner) layer must now be only a few nanometers thick, which makes it difficult to control the uniformity of such thin layers within the trench or via, especially when the aspect ratios approach 10. Additionally, the step of disposing a barrier layer into a patterned opening prior to filling adds cost and complexity to the semiconductor fabrication process.
Accordingly, there is a need for a process to fabricate metal barrier layers for semiconductor filling applications which occupy a small percentage of the volume of a patterned opening, such as a trench or via, in a dielectric. Moreover, there is a need for a process of forming barrier layers in such patterned openings, which do not reduce the size of the openings at all. Additionally, there is a need for a process of forming barrier layers which can eliminate the barrier deposition step all together prior to filling.